The invention relates to solid state image sensors, and specifically to a class of Virtual Phase (VP) image sensors that include in their fabrication process only a single layer of polysilicon deposition. The sensors may also incorporate Lateral Overflow Anti-blooming Drain (LOD) structures.
Standard CCD image sensors consist of pixel elements that include two or more gates fabricated by depositing more than one polysilicon layer on top of a suitable gate dielectric layer. The exception to this rule are devices fabricated by the VP technology, described in the U.S. Pat. No. 4,229,752 to Hynecek (1980), where charge is transferred from pixel to pixel by clocking only a single gate electrode. A CCD device that needs only a single gate for its operation offers an advantage in fabrication since all the electrodes of each CCD register in the entire image sensor array can be fabricated by depositing only a single polysilicon layer. This results in higher performance and in significant cost savings not only in manufacturing but also in device applications where fewer peripheral circuits, gate drivers, are needed. Among other advantages of the VP technology are low dark current due to the surface state pining effect and high Quantum Efficiency (QE) from deep UV to near IR spectral regions. Unfortunately the VP technology also has some disadvantages. In order to achieve the single electrode clocking, several ion implantation steps are incorporated into the process. This partially offsets the manufacturing cost savings and also makes the CCD charge transfer only unidirectional. The second disadvantage is in higher clocking voltages that have to be applied to these devices to accomplish an efficient charge transfer with a high charge well capacity.
It is thus desirable to develop a new CCD technology that retains the advantages of the VP concept and at the same time would minimize or eliminate disadvantages. In particular, a single polysilicon layer is a very attractive feature, since the single polysilicon deposition step is compatible with modern CMOS manufacturing technology and makes the on-chip CCD and CMOS system integration easier. The advantages of a CCD device with only a single polysilicon layer have also been recognized by others, as found in the article: xe2x80x9cPerformance of FT-CCD Image Sensor with Single Layer Poly-Silicon Electrodexe2x80x9d by Y. Okada, Y. Ohtsuru, S. Izawa, N. Taino, and M. Hamada. The article was published in the proceedings of: xe2x80x9c1999 IEEE Workshop on Charge Coupled Devices and Advanced Image Sensorsxe2x80x9d, paper R35, Jun. 10-12, 1999.
Thus it is the purpose of this patent to show how a modern CCD sensor can be manufactured using only a single polysilicon deposition step in its fabrication process while maintaining the low dark current and high quantum efficiency of the previously developed VP technology. Furthermore it will be shown that an efficient LOD anti blooming structure can also be incorporated into such a device and that it does not require a polysilicon gate for its proper function. And finally, it will be shown that a multidirectional charge transfer, as well as processing simplification, are obtained by splitting the single polysilicon gate into two or more independently clocked gate electrodes by very narrow gaps.
It is herein recognized that a need exists for solid state image-sensing devices that are fabricated on a suitable semiconductor substrate by incorporating only a single polysilicon deposition step in their fabrication processes. It is further recognized that a need exists that such devices also includes the LOD anti blooming drain structure, can be operated with low clocking voltages, and can maintain high performance such as the low dark current and high QE.
Generally, in one embodiment of the invention, a plan view of a typical image area CCD pixel is given with its corresponding cross sections in various stages of fabrication process. The key processing steps forming the essential features of the cell are described in detail. This includes the formation of vary narrow gaps that separate the polysilicon gate electrodes and the formation of the LOD anti-blooming drain structure.
In another embodiment of the invention, methods of incorporating the described cells into several typical image sensor architectures are given including their operation with the details of timing diagrams that improve the dark current performance and extend the operation dynamic range.
The invention thus provides many advantages including simplified fabrication processing with only a single level polysilicon deposition, lower clocking voltage operation, smaller parasitic electrode-to-electrode capacitances, high quantum efficiency, low dark current, LOD anti-blooming, extended dynamic range, and high flexibility of incorporation into many existing image sensor architectures. The single polysilicon deposition processing step makes the described CCD technology ideally suited for integration with modern CMOS circuits and systems.